
module top;
reg clk, rst;
wire [5:0] addr;
wire [7:0]data;
wire read;
simplecpu mcpu(data, rst, clk, read, addr);
mem mm(addr,read,data);
initial
 begin
clk=1;
rst=1;
#45
rst=0;
#5000 $stop;
end

always #20 clk=~clk;
endmodule